1. Field of the Invention
The present invention relates to a semiconductor memory device, and particularly to a discharge circuit in a nonvolatile semiconductor memory device such as a NAND flash memory.
2. Description of the Related Art
FIG. 1 shows a core portion of a NAND flash memory, and FIG. 2 shows a structure of a NAND cell 1 of FIG. 1. Further, FIG. 3 shows signal waveforms at the time of programming in the NAND flash memory of FIG. 1. Hereinafter, a programming operation of the NAND flash memory will be briefly described with reference to the drawings.
The discharge circuit 10 is controlled by a control signals CELLSRCVSS and CELLSRCVDDn, and the discharge circuit 11 is controlled by a control signals BLCRLVSS and BLCRLVDDn, respectively (Jpn. Pat. Appin. KOKAI Publication No. 8-87895).
As shown in the signal waveforms of FIG. 3, the cell source line CELLSRC is discharged to Vss via the discharge circuit 10. Substantially at the same timing, the bit lines 4 and 5 are equalized (during equalization period T2-T3, “High-Z”) and then are discharged to Vss via the bit line shield line BLCRL and the discharge circuit 11. FIG. 4 shows a row decoder 40 including a SGD driver which drives the select gate SGD, a WL driver which drives word lines WL0 to WL31, and a SGS driver which drives the select gate SGD. The inventors of the present application have found that when the cell source line CELLSRC and the bit lines 4, 5 are discharged, a PN junction in the row decoder 40 is biased in a forward direction to cause a bipolar operation. This is assumed to be based on the following reasons.
FIG. 5 shows a cross sectional view of the select gate SGS and the memory cell transistors in the NAND string. The select gate SGS has strong capacitive coupling of about 20% to 40% to the cell source line CELLSRC formed of a metal wiring M0. Further, the select gate SGD (not shown) has strong capacitive coupling of about 20% to 40% to a bit line formed of a metal wiring (not shown). Thus, when the cell source line CELLSRC and the bit lines 4 and 5 are rapidly discharged to Vss in the recovery operation, the potentials of the select gates SGS and SGD tend to lower from Vss, which is supplied from the driver side, to a negative potential. How much the select gates SGS and SGD lower depends on a discharge rate at which the cell source line CELLSRC and the bit lines are discharged to Vss, the strength of the capacitive coupling of the select gates SGS and SGD, a potential supply capability of the driver, and the like.